Retiming a lower frequency timing signal (or clock) by a higher frequency clock, when both signals are asynchronous to each other, is typically done by passing the lower frequency signal through a series of registers (e.g., flip-flops) that are clocked using the higher frequency clock. There is however, a certain probability of a metastability condition per register stage and the overall probability of metastability at the system output increases exponentially with each register stage used. The number of registers is established such that the Mean Time Between Failures (MTBF) rate is acceptably small. Unfortunately, the metastability condition brings with it the timing uncertainty of one high speed clock (possibly higher) since, during metastability, the output could be resolved at a given clock period or at the next. Although the output levels are defined, this timing error is unacceptable in some applications. A need thus exist in the art for a method for asynchronous clock retiming that can overcome some of the problems mentioned above.